DS1677E【PDF 15/18 页】IC CTRLR SYSTEM PORT 20-TSSOP

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Sheet目录1994

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DS1677

6 of 18

TIME OF DAY ALARM BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

SECONDS

MINUTES

HOURS

DAYS

DESCRIPTION

Alarm once per second.

Alarm when seconds match.

Alarm when minutes and seconds match.

Alarm when hours, minutes and seconds match.

Alarm when day, hours, minutes and seconds match.

SPECIAL PURPOSE REGISTERS

The DS1677 has two additional registers (control register and status register) that control the RTC and

interrupts.

CONTROL REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

EOSC

AIS1

AIS0

AIE

EOSC (Enable Oscillator). This bit, when set to logic 0 will start the oscillator. When this bit is set to a

logic 1, the oscillator is stopped and the DS1677 is placed into a low-power standby mode with a current

drain of less than 200nA when in battery-backup mode. When the DS1677 is powered by VCC, the

oscillator is always on regardless of the status of the EOSC bit; however, the RTC is incremented only

when EOSC is a logic 0.

WP (Write Protect). Before any write operation to the real time clock or any other registers, this bit

must be logic 0. When high, the write protect bit prevents a write operation to any register.

AIS0–AIS1 (Analog Input Select). These two bits are used to determine the analog input for the analog-

to-digital conversion. Table 2 lists the specific analog input that is selected by these 2 bits.

AIE (Alarm Interrupt Enable). When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF)

bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the

INT signal.

ANALOG INPUT SELECTION Table 2

AIS1

AIS0

ANALOG INPUT

NONE

AIN0

AIN1

AIN2

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